1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to scalable two-transistor memory devices and methods of fabricating the same.
2. Description of the Related Art
Scalable two-transistor memory (STTM) cells may offer advantages of both Dynamic Random Access Memory (DRAM) and flash memory devices. STTM cells are nonvolatile memory devices requiring no refresh, which may offer advantages such as high-speed operation, low power consumption, and high packing density.
FIG. 1 is an equivalent circuit diagram of a conventional STTM cell. FIG. 2 is a cross-sectional view illustrating the STTM cell structure shown in FIG. 1. The equivalent circuit diagram shown in FIG. 1 illustrates a single unit cell, while the STTM cell structure shown in FIG. 2 illustrates two unit cells that share a common source region.
Referring now to FIG. 1, the STTM cell includes two transistors: a planar transistor PT, and a vertical transistor VT that is formed on the planar transistor PT. The planar transistor PT includes a source region connected to a first word line 104 and a drain region connected to a sensing line 102. A floating gate conductive layer FG is formed on a channel forming region between the source region and the drain region on a gate insulating layer. The floating gate conductive layer FG forms the gate electrode for the planar transistor PT. The floating gate conductive layer FG also forms a drain region for the vertical transistor VT. The vertical transistor VT includes a multiple tunnel junction structure 110 formed on the floating gate conductive layer FG and a control gate conductive layer and a data line conductive layer respectively connected to a control line 106 and a second word line 108.
A cross-sectional view of the STTM cell of FIG. 1 will now be described with reference to FIG. 2. An active region defined by an isolation layer 204 is formed in a portion of a p-type well region 202 on a semiconductor substrate 200. A common source region 206 is formed in the active region, and a drain region 208 is formed in the active region on each side of the common source region 206. The common source region 206 is connected to the first word line 104 of FIG. 1, and the drain region 208 is connected to the sensing line 102 of FIG. 1. A region between the source region 206 and each drain region 208 forms a channel forming region 210 where an inversion layer channel may be formed. A gate insulating layer 212 is formed on the channel forming region 210, and a floating gate conductive layer 214 is formed thereon. The floating gate conductive layer 214 forms a gate electrode for the planar transistor PT. Accordingly, the source region 206, the drain region 208, the channel forming region 210, the gate insulating layer 212, and the floating gate conductive layer 214 form the planar transistor PT of FIG. 1.
Still referring to FIG. 2, a multiple tunnel junction structure MTJ is formed on the floating gate conductive layer 214. The multiple tunnel junction structure MTJ is formed by sequentially stacking a first tunnel barrier layer 216, a first channel conductive layer 218, a second tunnel barrier layer 220, a second channel conductive layer 222, and a third tunnel barrier layer 224. A data line conductive layer 226 connected to a data line (i.e., the second word line 108 shown in FIG. 1) and an insulating layer 228 are sequentially formed on the multiple tunnel junction structure MTJ. The floating gate conductive layer 214, the multiple tunnel junction structure MTJ, the data line conductive layer 226, and the insulating layer 228 are surrounded by a sidewall insulating layer 230. A control gate conductive layer 232 connected to the control line 106 is formed on the sidewall insulating layer 230. Accordingly, the floating gate conductive layer 214 forms a drain region, the multiple tunnel junction structure MTJ forms a channel region, the data line conductive layer 226 forms a source region, the sidewall insulating layer 230 forms a gate insulating layer, and the control gate conductive layer 232 forms a gate electrode for the vertical transistor VT of FIG. 1.
In a conventional STTM cell structure as described above, charges may be stored in the floating gate conductive layer 214 using a tunneling phenomenon produced by applying a predetermined voltage to the floating gate conductive layer 214. The charges may penetrate through tunnel barrier layers formed between the channel conductive layers of the vertical transistor VT, thereby forming a channel in the multiple tunnel junction structure MTJ in a vertical direction. As a result, performance of the STTM cell may not be degraded even when the widths of the floating gate conductive layer 214, multiple tunnel junction structure MTJ, and data line conductive layer 226 are reduced, because the channel is formed vertically. However, in the planar transistor PT, when the distance between the source region 206 and the drain region 208 is decreased, short channel effects may occur, thereby degrading performance. Although the source region 206 and the drain region 208 can be formed to a shallower junction depth to alleviate short channel effects, such an approach has its limits. Further, the resistance of the source region 206 and the drain region 208 may be increased, which may also degrade performance of the device.